The present invention relates to non-volatile flash memory devices and, more particularly, to a flash memory device of greater storage capacity compared with prior art flash memory devices. Specifically, the device includes a different number of bits per cell dependent on the predicted reliability of the cell.
Flash memory is a type of non-volatile memory. Non-volatile memory stores information on a silicon chip in a way that does not need power to maintain the information in the chip. If power to the chip is turned off, the information is retained without consuming any power. Flash memory is made in different forms including NOR flash and NAND flash. The names refer to the similarity of the interconnections between storage cells in the two types of flash memory to the well-known NOR and NAND logic circuits. A limitation of flash memory is that while flash memory can be read or programmed, for instance in NOR flash a byte or word at a time in a random access fashion, a block of memory must be erased at the same time. A block is the smallest chunk of memory that is erased in one operation. In NAND flash memory, the memory can be read or programmed in a random access fashion a page at a time. A block is typically much larger than a page in NAND flash.
Flash memory is based on the floating-gate metal oxide transistor which is essentially an NMOS transistor with an additional conductor suspended between the gate and source/drain terminals. Flash memory stores information in an array of transistors, called “cells”. Each cell is similar to a standard MOSFET transistor, but the cell has two gates instead of just one. One gate is the control gate (CG) like in other MOS transistors, and the second gate is a floating gate (FG) that is insulated by an oxide layer. The FG is between the CG and the substrate. Because the FG is isolated by the insulating oxide layer, any electrons placed on it get trapped there. Electrons on the FG modify, i.e. partially cancel out the electric field coming from the CG. The cell is “read” by applying a specific voltage on the CG. Electrical current either flows if the applied voltage is greater than a threshold voltage or otherwise electrical current does not flow, depending on the threshold voltage of the cell controlled by the number of electrons on the FG. The presence or absence of current is sensed and translated into 1's and 0's, reproducing the stored data.
Newer flash memory devices, sometimes referred to as multi-level cell devices (MLC), can store more than one bit per cell, by varying the number of electrons placed on the floating gate (FG) of a cell. In a multi-level cell device the amount of current is sensed, rather than simply the presence or absence of current. Two or more bits of data are stored in each cell by operating the individual cells with four or more programmable states. Three threshold breakpoint levels are necessary to define four different threshold states. Since an available operating range of the individual cells is divided into an increased number of states, the range of each state is smaller. In order to assure that the state of a cell programmed into a particular threshold range is accurately read, the programming is usually performed with an additional margin beyond the threshold breakpoint level. In MLC devices, because the separation between the storage states is smaller, storing more bits per cell reduces the reliability of any single bit. In most MLC devices the device manufacturer does not give the user any means to select the number of bits per cell in a given block, i.e the number of bits per cell is the same for all the cells in the device. In some cases the number of bits per cell can be reduced on parts of a device in order to achieve higher performance or higher reliability during programming. For example, a MLC flash may store two bits per cell in most of its blocks, but under software program control, store only one bit per cell in some blocks. MLC flash devices having different blocks within the same device storing different numbers of bits per cell have been disclosed in prior art. Representative prior art includes Lee et al. U.S. Pat. No. 5,930,167, Gonzales et al. U.S. Pat. No. 6,807,106, and Chen U.S. Pat. Nos. 6,456,528 and 6,717,847. Chen discloses switching blocks to a lower number of bits per cell when the blocks approach the end of their expected useful lifetime.
Reference is now made to FIG. 1 (prior art) a simplified drawing of a NAND flash memory device 10 including an array of cells 105. Cells 105 are accessed by word lines 103 connected to control gates of cells 105 and by bit lines 107 connected to array 10 at the drain side. Bit line 107 is selected by a bit line select (drain side) 109 and a bit line select (source side) 111. Typically, in some NAND flash devices, not all cells 105 have the same reliability. For example, cells that are closer to the bit line select (drain side) 109 are more sensitive to disturbance errors than other cells 105, while cells closer to the source side select 111 have better reliability characteristics. When designing a flash memory device the designer has to take into account that even the lower reliability cells 105 will be used for storing the maximal number of bits per cell the device specification allows, and therefore the characteristics of the poorest reliability cells dictate the number of bits per cell that the device will store in all cells 105. For instance, setting 4 bits per cell in all cells 105 for all word lines 105 would cause device 10 to fail its reliability specification due to the inferior reliability of certain cells 105.
There is thus a need for, and it would be highly advantageous to have a device of increased storage capacity that utilizes the highest number of bits that can be stored in each cell without compromising reliability of the device.